DocumentCode :
648677
Title :
GR-PA: A cost pre-allocation model for global routing
Author :
Nunes, Luis C. ; Reimann, Tiago ; Reis, R.
Author_Institution :
Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
fYear :
2013
fDate :
7-9 Oct. 2013
Firstpage :
134
Lastpage :
137
Abstract :
This work presents methods to identify and treat circuit areas that have high overflow and interconnect demand, during global routing step. In that way, two cost pre-allocation techniques are presented: the first is applied during the pre-routing congestion estimation step of the global routing flow; the second technique will act during the iterative routing phase, where the the congestion is updated on each routing round and the congestion hot spots can be identified. Since the congestion hot spots are identified, a cost calibration step is executed using the proposed congestion look-ahead techniques. The focus of these algorithms is to speed up the convergence of the global routing solution while trying to reduce the side effects in wire length. Our experiments shows a speed up of up to 1.357x with 1.39% of maximum increase in wirelength when compared to the reference implementation for the ISPD 2008 benchmarks.
Keywords :
integrated circuit interconnections; network routing; GR-PA; congestion hot spots; congestion look-ahead techniques; cost calibration step; cost pre-allocation model; global routing step; interconnect demand; iterative routing phase; pre-routing congestion estimation step; wire length; EDA tools; algorithm tuning; cost calibration; global routing; microelectronics; physical design; routing grid;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Very Large Scale Integration (VLSI-SoC), 2013 IFIP/IEEE 21st International Conference on
Conference_Location :
Istanbul
Type :
conf
DOI :
10.1109/VLSI-SoC.2013.6673264
Filename :
6673264
Link To Document :
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