Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects

In nano-scale process, shallow trench isolation (STI) stress and well proximity effect (WPE) affect the threshold voltage of MOSFET as well as the performance of the system-on-chips (SoC). As one of the most sensitive and highest density circuit, SRAMs must be designed considering the stress effect analysis. The variation of the stress effect causes dramatical change of the threshold voltage especially beyond 90nm process. In this paper, we present an SRAM macro design methodology dealing with a significant trade-off among area, leakage power and delay by introducing non-uniform parameterized SRAM cells. Experimental results show that this technique can reduce the leakage power and macro area of a 32×64 SRAM by 12.5% and 18.2% respectively.