Static energy minimization of 3D stacked L2 cache with selective cache compression

Three-dimentional (3D) integration is one of the most promising approaches to increase cache bandwidth and to reduce the wire length and thereby, the delay and transmission power consumption. However, high power density in 3D IC due to dense integration incurs significant leakage current increment which leads to high static energy consumption. The leakage energy consumption of 3D-stacked cache memory is more serious than that of conventional cache memory in 2D ICs. In this paper, we propose a selective cache compression technique coupled with power gating to reduce the static energy consumption of 3D-stacked SRAM cache. Cache blocks are selected to be compressed in runtime according to the cache access pattern, so that the decompression overhead is reduced. The experimental results show that our method reduces energy consumption by up to 40% (22% on average) with negligible performance overhead compared with the conventional cache management policy.