A new dimension of parallelism in ultra high throughput LDPC decoding

In modern communication systems the required data rates are continuously increasing. High speed transmissions can easily generate throughputs far beyond 1 Tbit/s. To ensure error free communication, channel codes like Low-Density Parity Check (LDPC) codes are utilized. However state-of-the-art LDPC decoders can process only data rates in the range of 10 to 50 Gbit/s. This results in a gap in decoder performance which has to be closed. Therefore we propose a new ultra high speed LDPC decoder architecture. We show that our architecture significantly reduces the routing congestion which poses a big problem for fully parallel, high speed LDPC decoders. The presented 65nm ASIC implementation runs at 257 MHz and consumes an area of 12 mm²The resulting system throughput is 160 Gbit/s, it is the fastest LDPC decoder which has been published up to now. At the same time we show that extremely parallel architectures do not only increase the maximum throughput but also increase area and power efficiency in comparison to state-of-the-art decoders.