DocumentCode :
649101
Title :
Arithmetic circuits using new single-phase partially-adiabatic logic family
Author :
Cutitaru, Mihail ; Belfore, Lee A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Old Dominion Univ., Norfolk, VA, USA
fYear :
2013
fDate :
4-7 Aug. 2013
Firstpage :
13
Lastpage :
16
Abstract :
This paper proposes a single-phase partially-adiabatic logic family and compares its energy characteristics with other adiabatic families by simulating a full-adder (FA) and an 8-bit carry-lookahead adder (CLA). Full-adder simulation results show that the proposed family uses up to 79% less energy compared to its CMOS equivalent and up to 67% less than other adiabatic implementations. The proposed 8-bit adiabatic CLA performs at least as well as the next best implementation while using a single phase clock instead of a four-phase clock.
Keywords :
adders; carry logic; clocks; logic circuits; CLA; arithmetic circuits; carry-lookahead adder; energy characteristics; full-adder; single phase clock; single-phase partially-adiabatic logic family; word length 8 bit;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location :
Columbus, OH
ISSN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2013.6674573
Filename :
6674573
Link To Document :
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