Arithmetic circuits using new single-phase partially-adiabatic logic family

This paper proposes a single-phase partially-adiabatic logic family and compares its energy characteristics with other adiabatic families by simulating a full-adder (FA) and an 8-bit carry-lookahead adder (CLA). Full-adder simulation results show that the proposed family uses up to 79% less energy compared to its CMOS equivalent and up to 67% less than other adiabatic implementations. The proposed 8-bit adiabatic CLA performs at least as well as the next best implementation while using a single phase clock instead of a four-phase clock.