• DocumentCode
    649102
  • Title

    Sleep Convention Logic using partially slept function blocks

  • Author

    Palangpour, Parviz ; Smith, Scott C.

  • Author_Institution
    Dept. of Electr. Eng., Univ. of Arkansas, Fayetteville, AR, USA
  • fYear
    2013
  • fDate
    4-7 Aug. 2013
  • Firstpage
    17
  • Lastpage
    20
  • Abstract
    Sleep Convention Logic (SCL) is a self-timed pipeline style that offers inherent power-gating, resulting in ultra-low static power consumption. After each pipeline stage has processed new data, control logic asserts a sleep signal causing the entire pipeline stage to be power-gated until the next data arrives. Due to the aggregate sleep capacitance for each pipeline stage, there is an energy overhead for waking and sleeping the pipeline stages. In this paper, an alternative is presented in which only a portion of each pipeline stage is put to sleep. This reduces the aggregate sleep capacitance for each pipeline stage, resulting in reduced dynamic energy consumption.
  • Keywords
    logic circuits; low-power electronics; pipeline arithmetic; power consumption; SCL; control logic; dynamic energy consumption; energy overhead; partially slept function blocks; pipeline stage; power gating; self-timed pipeline style; sleep capacitance; sleep convention logic; sleep signal; ultralow static power consumption;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
  • Conference_Location
    Columbus, OH
  • ISSN
    1548-3746
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2013.6674574
  • Filename
    6674574