Testing reversible adder/subtractor for missing control points

Testing reversible circuits is a challenging issue. A commonly used technology related fault model in reversible gate is missing control points of reversible gates. In this paper we address this type of fault in reversible adder/subtractor circuit and present an efficient way to detect and identify the location of the faults. The regular structure of adder/subtractor facilitates the testing of such circuits and we show that only three test vectors are sufficient to test for n-bit adder/subtractor with 100% fault coverage. Moreover, with proper sequence of input test vectors it is possible to find the fault location.