Novel clock gating techniques for low power flip-flops and its applications

Two new clock gated flip-flops are presented. The designs are based on new clock gating approaches to reduce the consumption of clock signal´s switching power. They operate with no redundant clock cycles and have reduced number of transistors to minimize the overhead and to make it suitable for data signals with higher switching activity. The proposed flip-flops are used to design 8-bit successive approximation register. This application has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using Spectre. Simulations with the inclusion of parasitics have shown the effectiveness of the new approaches on power consumption and transistor count.