FLNR: A fast light-weight NoC router for FPGAs

Currently, FPGAs serve as Field-Programmable-Systems-on-Chip (FPSoCs) and are widely used to implement computationally intensive real world applications. As the number of components in FPSoCs increase, the interconnect schemes based on Network-on-Chip (NoC) approach are increasingly being used to overcome the deficiencies of the traditional bus- based and point-to-point interconnect schemes. The router is a key component that greatly impacts the performance and cost of an NoC. In this paper we present FLNR, a fast light-weight NoC router designed for FPGAs. It is a 5-port packet switched wormhole router that uses a deterministic XY Routing algorithm and round robin arbitration scheme. The size of the input buffers and the flit size are parameterizable. We used novel techniques to achieve good speed performance while minimizing the area used. The number of control fields in a packet is minimized to reduce the size of buffers used. Credit based flow control is used to reduce the number of clock cycles required for transferring each flit. Both edges of the clock are used to implement router operations thereby speeding up the router. FLNR is compared to other proposed routers based on three metrics: area, frequency and zero load latency. Synthesis results and zero load latency evaluations show that our router is significantly superior to widely referenced, previously proposed routers.