Design of high speed high-voltage drivers based on stacked standard CMOS for various supply voltages

This paper presents a new concept for reducing on-resistance of high-voltage drivers based on stacked MOSFETs for various supply voltages. A theory to calculate gate voltages of an N-stacked CMOS driver to drive the maximum drain current at a minimum on-resistance is introduced. According to the calculated gate voltages, a circuit design methodology is described to generate them. The principle is applied on a 2-stack CMOS driver in 65-nm with a nominal voltage of the I/O-devices of 2.5 V. For various supply voltages, simulations show an improvement of 27%-86% reduction of the initial on-resistance and approximately 16%-83% improved rise and fall times of the output signal at a load capacitance of 150 pF if compared to previous work. The principle can be applied to N-stack driver transistors.