Novel implementation of full adder based scaling in Residue Number Systems

The need for faster digital circuitry has turned the researchers to alternative number systems and arithmetic level modifications. One such number system being used is the Residue Number System (RNS). With computationally fast addition, subtraction and multiplication it has become widely used in many vast areas of Digital Signal Processing (DSP). The drawback to using RNS is that it has several computationally slow and resource intense operations, most notably, scaling and conversion. This paper presents a novel implementation of three moduli set {2ⁿ - 1, 2ⁿ, 2ⁿ + 1} scaling system and the constant scaling factor. The main difference of the proposed system to existing scaling systems includes elimination of the overhead conversion system and employing modular reducers in implementation of the design. Many algorithms for fast scaling in RNS exist, but this paper will focus on developing a particular algorithm using adder based techniques.