Efficient calibration scheme for high-resolution pipelined ADCs

This paper describes a background calibration technique that linearizes pipelined ADCs by correcting for errors in the digital domain. This also relaxes the requirements for the analog components and enables power and area savings. The calibration technique doesn´t require a separate reference ADC that samples the input, nor the generation of digital correlation signals or extra analog calibration components. The calibration technique is robust and easily implementable in any digital technology. The implementation of the digital calibration algorithm requires minimal digital resources and less than 1% of the overall ADC power consumption.