DocumentCode
649266
Title
Digital calibration of inter-stage nonlinear errors in pipelined SAR ADC
Author
Yuan Zhou ; Yun Chiu
Author_Institution
Texas Analog Center of Excellence, Univ. of Texas at Dallas, Dallas, TX, USA
fYear
2013
fDate
4-7 Aug. 2013
Firstpage
677
Lastpage
680
Abstract
A digital calibration technique to linearize the residue amplifier in pipelined SAR ADC based on Independent Component Analysis (ICA) is presented. The proposed technique utilizes a single, one-bit pseudorandom noise (PN) to simultaneously identify all coefficients of a correction polynomial. Behavioral simulation results demonstrate the effectiveness of the technique, in which the SNDR and SFDR performance of a 12-bit pipelined SAR ADC is improved from 54 dB and 69 dB to 72 dB and 100 dB, respectively. Some circuit design details are included for the PN injection circuit as well as the digital calibration logic.
Keywords
amplifiers; analogue-digital conversion; calibration; circuit simulation; independent component analysis; integrated circuit design; integrated circuit noise; pipeline processing; ICA; PN injection circuit; SFDR; SNDR; behavioral simulation; circuit design; correction polynomial; digital calibration logic; independent component analysis; inter-stage nonlinear errors; one-bit pseudorandom noise; pipelined SAR ADC; residue amplifier; word length 12 bit;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on
Conference_Location
Columbus, OH
ISSN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2013.6674739
Filename
6674739
Link To Document