Design considerations for a multi-integrator architecture for random demodulation compressive sensing

The random demodulator architecture is a compressive sensing based receiver that allows the reconstruction of frequency-sparse signals from measurements acquired at a rate below the signal´s Nyquist rate. This in turn results in tremendous power savings in receivers because of the direct correlation between the power consumption of analog-to-digital converters (ADCs) in communication receivers and the sampling rate at which these ADCs operate. In this thesis, we propose design techniques for a robust and efficient random demodulator. The resetting mechanism can pose challenges in practical settings that can degrade the performance of the random demodulator. We propose practical approaches to mitigate the effect of resetting and propose resetting schemes that provide robust performance.