A reformulated systematic resampling algorithm for particle filters and its parallel implementation in an application-specific instruction-set processor

Particle filters (PFs) are computationally intensive, which prevents them from being widely used in some real-time applications with high throughput requirements. A parallel implementation is a feasible approach to enable using PFs in these applications. However, effective resampling algorithms such as the Systematic Resampling (SR) algorithm are sequential in nature. In this paper, we propose a new form of the SR algorithm suitable for parallel implementation in an Application-Specific Instruction-set Processor (ASIP). Six custom instructions were designed for this reformulated SR algorithm. Experimental results show that the ASIP implementation of the reformulated SR algorithm, with four weights calculated in parallel, and eight categories defined by uniformly distributed numbers that are compared simultaneously to achieve a 30.6× speedup over the serial SR algorithm in a general-purpose processor. This comes at a cost of only 54K additional gates, or 68% overhead to be added to a base processor with 79K gates.