Fully-coupled 3D electro-thermal field simulator for chip-level analysis of power devices

The paper presents a novel approach to modelling static and dynamic electro-thermal effects in large integrated and discrete semiconductor power devices. Electrical and thermal equations are solved simultaneously and selfconsistently from a single set of equations. A high spatial resolution allows accurate modelling of metal layers as required for advanced integrated BCD technologies. The simulator uses a well-adapted mesh for the substrate, which is important for the simulation of the temperature. Thus, both the voltage drop in the on-chip metallization as well as the device temperatures can accurately be determined without sacrificing accuracy or limiting the applicability of the simulator to special cases. Electrical and thermal conductivities of both metal and substrate are temperature dependent. Measurement and simulation results for test chips and real DMOS driver stages with small integrated temperature sensors are presented. An excellent match is observed even for very high temperatures exceeding 300°C. The tool integrates easily in an industrial design environment with direct import of GDS layout and ITF technology data.