• DocumentCode
    649565
  • Title

    Efficient on-chip vector processing for multicore processors

  • Author

    Beldianu, Spiridon F. ; Ziavras, Sotirios G.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
  • fYear
    2013
  • fDate
    23-24 Oct. 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Per-core vector support in multicores is not efficient since applications rarely sustain high DLP. We present two Power Gating (PG) schemes to dynamically control Vector co-Processors (VPs) shared by cores. ASIC and FPGA modeling show that PG can reduce the energy by 33% while maintaining high performance.
  • Keywords
    application specific integrated circuits; coprocessors; field programmable gate arrays; multiprocessing systems; vector processor systems; ASIC modeling; DLP; FPGA modeling; PG schemes; multicore processors; on-chip vector processing; per-core vector support; power gating schemes; vector coprocessors; multicores; vector processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System on Chip (SoC), 2013 International Symposium on
  • Conference_Location
    Tampere
  • Type

    conf

  • DOI
    10.1109/ISSoC.2013.6675260
  • Filename
    6675260
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=649565