ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores

Field Programmable Gate Arrays (FPGA) are widely used to accelerate parallel applications by specialized hardware. Especially for data flow intensive applications FPGAs are very well suited to design application specific data paths with a certain degree of parallelism. Since most of applications also need control flow, the most common method is to design complex state machines that are realized in hardware. However, this often leads to very high and inefficient resource utilization on the target architecture for design parts that are not performance critical nor relevant for more efficient realizations. In this paper, we propose a generic VLIW-inspired Slot Architecture (ViSA), which combines two efficient objectives, the performance of parallel hardware and the low area utilization of custom processors. Furthermore, we introduce the methodology for mapping and debugging applications on the efficient ViSA architecture.We present experimental results of two corner case applications showing that our approach is suitable for ultra low power as well as high performance computing. Using the presented co-design methodology, we will conclude that ViSA enables the realization of multi-objective design spaces for various target domains. ViSA has extreme throughput at low operating frequencies leading to significant power and energy savings over state of the art architectures.