20-Bit RISC and DSP System Design in an FPGA

Author

Tomar, Amit Kumar Singh ; Jain, R.

Author_Institution

Lakshmi Narain Coll. of Technol., India

Volume

16

Issue

2

fYear

2014

fDate

Mar.-Apr. 2014

Firstpage

16

Lastpage

20

Abstract

These days, most microprocessor and microcontroller designs are based on a Reduced Instruction Set Computer (RISC) core, and many operations - such as discrete cosine transform (DCT), inverse DCT, discrete Fourier transform (DFT), and fast Fourier transform (FFT)--are performed by a digital signal processor (DSP) system. Here, the authors present the design of a RISC and DSP system that uses very high-density logic (VHDL) and a field-programmable gate array (FPGA). This RISC is a 20-bit processor.

Keywords

digital signal processing chips; field programmable gate arrays; integrated circuit design; reduced instruction set computing; 20-Bit RISC; DSP system design; FPGA; VHDL; digital signal processor system; field-programmable gate array; microcontroller designs; microprocessor designs; reduced instruction set computer core; very high-density logic; Digital signal processing; Discrete Fourier transforms; Discrete cosine transforms; Field programmable gate arrays; Logic gates; Reduced instruction set computing; Registers; ALU; CPU; CU; FPGA; GPR; IR; MACs; PC; RISC; RS; VLIW; arithmetic logic unit; control unit; field-programmable gate array; general-purpose register; instruction register; multiply and accumulates; program counter; reduced instruction set computer; register set; scientific computing; very large instruction word;

fLanguage

English

Journal_Title

Computing in Science & Engineering

Publisher

ieee

ISSN

1521-9615

Type

jour

DOI

10.1109/MCSE.2013.20

Filename

6468030