High throughput pipelined implementation of pulse width modulation on FPGA

Most of the physical systems applications require a real-time operation to interface high speed restraints. We present an equivalent pipelined PWM architecture working to provide the highest throughput up to date through inserting some registers in appropriate points making the delay shortest, when implementing the byte transformation in one clock period. The register is included in the final stage of both existing and proposed architecture. Higher density programmable logic device such as FPGA[1] can be used to integrate large amounts of logic in a single IC. FPGA becomes one of the most successful of technologies for developing the systems which require a real time operation. Pulse width modulation (PWM) has been widely used in power converter control. The proposed PWM generation unit is based on a specially designed with pipelined, synchronous binary counter, resulting in maximum PWM frequencies with a lower delay. So the speed will be increase. While the PWM unit can be easily interfaced to a microcontroller or DSP system. The contribution of this paper is the development of high frequency PWM generator architecture for power converter control using FPGA. The resulting PWM frequency depends on the target FPGA device speed grade and the duty cycle resolution requirements.