Simulation of TID effect on floating gate cells

This paper discusses the electrical simulation of Non-Volatile Memory Cells, based on the Floating Gate Cells, and aiming at the evaluation of Total Ionizing Dose (TID) effect of this memory cell. An electrical model based on simple electric elements is implemented to allow the simulation of the floating gate using standard electrical simulations tools (e.g. Spice). For the evaluation of TID effects the electrical parameters of the MOS transistor (i.e threshold voltage and leakage current between de source and drain terminals) are varied according to experimental data from the literature.