DocumentCode
651297
Title
VLSI techniques for fault secure encoder and decoder in nano memory applications
Author
Chandrasekar, M. ; Dhinakar, P.
Author_Institution
VKS Coll. of Eng. & Technol., Desiyamangalam, India
fYear
2013
fDate
2-3 July 2013
Firstpage
1
Lastpage
4
Abstract
Memory are largely affected by soft errors and do so the the encoder and decoder circuitry around the memory. In this paper we address the issue by going for a newly designed FSD with a new class of error correcting codes named EG-LDPC. The mechanism by which the codes detect faults is clearly demonstrated. Larger codes have been used in nano scale and brings about more reliability and low area overhead.
Keywords
error correction codes; fault tolerance; integrated circuit design; integrated circuit reliability; nanoelectronics; parity check codes; semiconductor storage; EG-LDPC; VLSI techniques; error correcting codes; fault secure decoder; fault secure encoder; low density parity check code; nanomemory applications; soft error;
fLanguage
English
Publisher
ieee
Conference_Titel
Optical Imaging Sensor and Security (ICOSS), 2013 International Conference on
Conference_Location
Coimbatore
Print_ISBN
978-1-4799-0935-3
Type
conf
DOI
10.1109/ICOISS.2013.6678434
Filename
6678434
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