Title :
A Power Model Combined of Architectural Level and Gate Level for Multicore Processors
Author :
ManMan Peng ; Yan Hu
Author_Institution :
Key Lab. for Embedded & Network Comput. of Hunan Province, Hunan Univ., Changsha, China
Abstract :
Low power consumption is becoming a critical factor for multicore processors. As the multicore processor design complexity increases, power estimation for multicore processors has gained more importance. This paper presents a new power model combined of architectural level and gate level for multicore processors. The model maps the multicore processors to a combination of building blocks, and estimates the gate-level power of these blocks using parameterized RTL. Then, the power numbers are made in the form of look-up tables, and integrated in architecture simulators. The experiments show that for peak power estimation, an excellent accuracy has been reached and simulation performance is greatly improved compared to the gate level.
Keywords :
multiprocessing systems; power aware computing; table lookup; architectural level; architecture simulators; gate-level power; look-up tables; low power consumption; multicore processor design complexity; parameterized RTL; power model; Analytical models; Computational modeling; Hardware; Logic gates; Multicore processing; Program processors; Random access memory; Multicore processors; architectural level; gate level; power modeling;
Conference_Titel :
Trust, Security and Privacy in Computing and Communications (TrustCom), 2013 12th IEEE International Conference on
Conference_Location :
Melbourne, VIC
DOI :
10.1109/TrustCom.2013.204