Celerity Hardware Implementation of the AES with Data Parallel and Pipelining Architecture inside the Round Function

Since it was accepted as the replacement of the Data Encryption Standard (DES) and 3 DES by NIST in 2001, the AES has played a major role in various security-constrained applications. Many applications are power-saving, resource constrained and require high-speed. AES is precisely suitable for being implemented in both software and hardware applications. Hardware implementation of AES has the advantage of increased throughput and better security. On the basis of those facts, in this paper, different hardware architectures of AES have been presented and surveyed. And we present a way of data parallel to deal with the bulk data of plaintext or cipertext, which brings lower clock cycles and increased working frequencies. Pipelining architecture inside the round function also contributed a lot to the promotion of data throughput. Moreover, the key schedule algorithm is pipelined to get the speedup, and the S-boxes which are based on look-up tables (LUTs) could be area-efficient. By conducting ALTERA FPGA realization and ModelSim simulation, we analyze the performance relating to the Slice registers, gate-level netlists, memory, Slice LUTs and so on.