Comparison of a 30nm Tunnel Field Effect Transistor and CMOS Inverter Characteristics

Author

Aswathy, M. ; Biju, Nitha M. ; Komaragiri, Rama

Author_Institution

Dept. of ECE, Nat. Inst. of Technol., Calicut, India

fYear

2013

fDate

29-31 Aug. 2013

Firstpage

149

Lastpage

152

Abstract

Tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at deca-nanometer dimensions. Tunneling currents are no longer considered as unwanted parasitics in these devices. In this work, the device architecture and performance of both n-type and p-type TFETs with a channel length of 30nm are simulated and studied. Mixed mode simulation of TFET inverter and a comparison with CMOS inverter characteristics show that TFET inverter doesn´t need level shifting at the output and can succeed CMOS digital applications.

Keywords

CMOS integrated circuits; field effect transistors; mixed analogue-digital integrated circuits; tunnel transistors; CMOS digital applications; CMOS inverter characteristics; MOSFET; TFET inverter; decananometer dimensions; n-type TFET; p-type TFET; size 30 nm; tunnel field-effect transistor; tunneling currents; CMOS integrated circuits; Inverters; Logic gates; MOSFET; Threshold voltage; Tunneling; Band-to-Band Tunneling; CMOS Inverter; Mixed mode device simulations; Tunnel Field Effect Transistor; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Advances in Computing and Communications (ICACC), 2013 Third International Conference on

Conference_Location

Cochin

Type

conf

DOI

10.1109/ICACC.2013.36

Filename

6686358