High Speed VLSI Architecture for Squaring Algorithm Using Retiming Approach

An innovative squaring Algorithm is proposed which solves the problem of finding the Squaring large binary numbers. The foundation of the algorithm lies in an ancient Vedic algorithm. The resulting n-bit squaring architecture translated into hardware. With the proposed architecture using retiming technique the optimizations for large binary number is achieved. The essential idea of retiming is to relocate latch boundaries to balance the delay of each stage. In this paper, we used a method for finding a feasible retiming to optimize a CDFG to meet a smallest iteration period. The production data rates and predictable execution time is model by CDFG graph. The proposed squaring algorithm is significant savings in time when compared with a special case of formula based on Dwandwayoga which means duplex. Duplex of a digit is calculated based on Urdhva-tiryagbhyam. The performance of the proposed algorithm is measured in terms of power and time and it is much better than the Dwandwayoga [8, 17] squaring algorithm. The design is simulated using NCsim from cadence and synthesize the design using RTL Compiler from the cadence EDA tool. The design is implemented using the 90nm standard cell technology Libraries.