Extension of the load-line theory by investigating the impact of the knee-voltage on output-power and efficiency

The standard load-line theory for power amplifier (PA) design becomes inaccurate when the ratio of the transistor´s knee-voltage to the supply voltage gets larger than one. This is often the case for sub-micron CMOS PA designs due to low breakdown voltage. Based on simple geometrical reasoning the load-line theory is generalized to include these cases. The optimum load impedance that results in maximum output power, the maximum power achieved, and the corresponding efficiency are derived in closed form. The efficiency can be improved by backing off the output power. The trade-off between output power and simultaneously achievable efficiency as a function of the knee-voltage is discussed.