Optimization methods and circuit topologies for low-power analog filters

This paper presents several solutions for reducing the power consumption of analog filters, from optimizing their transfer functions using tailored genetic algorithms to novel circuit topologies and effective transistor-level implementations. First, transfer functions are obtained that provide same attenuation as their classical-approximation counterparts, but have lower order; next, the transfer function of a cascaded filter is optimized considering implementation-related requirements, such as minimizing the quality factor of the biquads; next, an effective way to implement tunable single - OA biquads is presented. As an application, the design of the channel filter for a Zero-IF UWB receiver, with 250 MHz cut-off frequency and over 30dB rejection of the 530 MHz blocker, is briefly discussed.