A 10.6μm × 10.6μm CMOS SPAD with integrated readout

Author

Al Mamun, Khandaker A. ; Habib, Mohammad Habib Ullah ; Bishai, David ; McFarlane, Nicole

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of Tennessee, Knoxville, TN, USA

fYear

2013

fDate

3-6 Nov. 2013

Firstpage

1

Lastpage

4

Abstract

Single photon avalanche diodes (SPAD) are sensitive optical sensing tools. Incoming photons trigger avalanche events resulting in large device currents. In this paper, we show experimental results for a 10.6 μm × 10.6 μm perimeter gated SPAD with integrated readout circuitry in 0.5 μm 2 poly, 3 metal standard CMOS process. The dark count rate demonstrates a functional relationship with the gate and the excess bias voltage. A compact readout topology is used which takes advantage of the Miller effect to reduce the readout area footprint, thus increasing the pixel fill factor.

Keywords

CMOS integrated circuits; avalanche diodes; readout electronics; CMOS SPAD; Miller effect; avalanche events; bias voltage; compact readout topology; dark count rate; metal standard CMOS process; pixel fill factor; readout area footprint; readout circuitry; sensitive optical sensing tools; single photon avalanche diodes; Breakdown voltage; Capacitors; Delays; Electric breakdown; Logic gates; Photonics; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

SENSORS, 2013 IEEE

Conference_Location

Baltimore, MD

ISSN

1930-0395

Type

conf

DOI

10.1109/ICSENS.2013.6688553

Filename

6688553