A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package

This paper presents a novel scheme for silicon interposer testing. Testing interpose is difficult due to the large number of nets to be tested and small number of test access ports. Previous methods can only achieve limited fault coverage for open faults. We propose to include a test interposer that is contacted with the interposer under test in the testing process. Combining these two interposers will provide access to nets that are not normally accessible; thus, most or all nets become testable. Furthermore, both open and short faults in the interconnect structure can be tested. The efficiency of the proposed test scheme is mainly affected by the structure of test interposer; thus, algorithms for the generation of optimized test interposers are explored. Experimental results show that all faults can be efficiently tested with the proposed method.