Single Test Clock with Programmable Clock Enable Constraints for Multi-clock Domain SoC ATPG Testing

This paper proposes a method to enable single test clock in testing multi-clock domain design. Clock gating DFT is added to allow selecting clocking per clock domain basis. Selecting clocking scheme is further controlled by analyzing independent and synchronous clock group, translating clock group information into virtual circuit to guide ATPG generation process. The proposed solution enables fewer ATPG generation iteration which helps to reduce test pattern count and optimize ATPG run time.