Multi-histogram ADC BIST System for ADC Linearity Testing

Author

Koay Soon Chan ; Nordin, Nuzrul Fahmi ; Kim Chon Chan ; Terk Zyou Lok ; Chee Wai Yong

Author_Institution

Marvell Semicond. Sdn. Bhd., Nibong Tebal, Malaysia

fYear

2013

fDate

18-21 Nov. 2013

Firstpage

213

Lastpage

214

Abstract

This paper describes an ADC BIST system that utilizes a modified linear ramp histogram approach to test the linearity of an ADC with 10 bits of resolution on a System-On-Chip (SoC). The system tests the differential non-linearity (DNL) and Integral Non-linearity (INL) of an ADC. The ADC is tested in sections using a small amplitude triangle wave which is generated by charging and discharging an on-chip capacitor. This is an alternative solution to test an ADC when ADC-DAC loopback testing is not feasible. Both the ADC and BIST are designed in the 40 nm process node. Simulation results show that the BIST is capable of testing a 10-bit ADC.

Keywords

analogue-digital conversion; built-in self test; capacitors; integrated circuit testing; system-on-chip; ADC linearity testing; DNL; INL; SoC; differential nonlinearity testing; integral nonlinearity testing; modified linear ramp histogram approach; multihistogram ADC BIST system; on-chip capacitor; size 40 nm; small amplitude triangle; system-on-chip; word length 10 bit; Built-in self-test; Capacitors; Histograms; Linearity; Simulation; System-on-chip; ADC BIST; ADC linearity test; Built-in Self-test; Histogram testing; Triangle wave;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (ATS), 2013 22nd Asian

Conference_Location

Jiaosi Township

ISSN

1081-7735

Type

conf

DOI

10.1109/ATS.2013.47

Filename

6690643