A 446.6K-gates 0.55–1.2V H.265/HEVC decoder for next generation video applications

Author

Chang-Hung Tsai ; Hsiuan-Ting Wang ; Chia-Lin Liu ; Yao Li ; Chen-Yi Lee

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2013

fDate

11-13 Nov. 2013

Firstpage

305

Lastpage

308

Abstract

An architecture of H.265/HEVC video decoder for next generation video applications is presented. By exploiting near-lossless data compression and Sharing Above Line Buffer (SALB) schemes, both memory bandwidth and on-chip storage can be reduced. Moreover, cross-stage scheduling is applied to the 4-stage decoding pipeline to minimize idle computations. Fabricated in 90nm 1P9M CMOS process, the test chip of the proposed H.265/HEVC video decoder occupies an area of 1.60×1.98mm² to achieve 1080p@30fps and 720p@30fps realtime decoding with power consumption of 36.90 and 9.57mW.

Keywords

CMOS integrated circuits; buffer storage; data compression; pipeline processing; scheduling; video coding; 4-stage decoding pipeline; CMOS process; H.265/HEVC video decoder; SALB scheme; both memory bandwidth; cross-stage scheduling; near-lossless data compression; next generation video applications; on-chip storage; power 36.9 mW; power 9.57 mW; power consumption; realtime decoding; sharing above line buffer scheme; voltage 0.55 V to 1.2 V; Bandwidth; Decoding; Encoding; Logic gates; Random access memory; Streaming media; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian

Conference_Location

Singapore

Print_ISBN

978-1-4799-0277-4

Type

conf

DOI

10.1109/ASSCC.2013.6691043

Filename

6691043