• DocumentCode
    659021
  • Title

    Leveraging rule-based designs for automatic power domain partitioning

  • Author

    Agarwal, Abhishek ; Arvind

  • Author_Institution
    CSAIL, Massachusetts Inst. of Technol. Cambridge, Cambridge, MA, USA
  • fYear
    2013
  • fDate
    18-21 Nov. 2013
  • Firstpage
    326
  • Lastpage
    333
  • Abstract
    Leakage power reduction through power gating requires considerable design and verification effort. We present a scheme which uses high-level design description to automatically generate a collection of fine-grain power domains and associated control signals. We also describe a method of collecting the dynamic activity characteristics of a domain, viz. total inactivity and frequency of inactive-active transitions, which are necessary to decide the domain´s suitability for power gating. Our automated power-gating technique provides power savings without exacerbating the verification problem because the power domains are correct by construction. We illustrate our technique using two wireless decoder designs.
  • Keywords
    high level synthesis; power aware computing; automated power-gating technique; automatic power domain partitioning; fine-grain power domains; high-level design description; inactive-active transitions; leakage power reduction; power domains; power savings; rule-based designs; wireless decoder designs; Clocks; Color; Decoding; Logic gates; Reed-Solomon codes; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design (ICCAD), 2013 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2013.6691139
  • Filename
    6691139