Power efficient odd parity generator & checker circuits

Author

Vanlalchaka, Reginald H. ; Roy, Sandip

Author_Institution

Dept. of Electron. & Commun. Eng., Tezpur Univ., Tezpur, India

fYear

2013

fDate

13-14 Sept. 2013

Firstpage

65

Lastpage

69

Abstract

This paper presents three bit odd parity generator and detector circuits based on low power adiabatic logic technique. The paper proposes a new design approach which is being derived from CMOS. A simulative investigation on the proposed circuit has been carried out in NI Multisim at 0.5μm CMOS technology with L=0.5μm and W=1.25μm. The power consumption is compared with conventional CMOS and two popular standard 2PASCL and Adiabatic array logic technique which shows great improvement in power dissipations.

Keywords

CMOS logic circuits; detector circuits; 2PASCL; CMOS technology; low power adiabatic array logic technique; odd parity checker circuits; odd parity detector circuits; power efficient odd parity generator; size 0.5 mum; size 1.25 mum; word length 3 bit; Arrays; CMOS integrated circuits; Clocks; Generators; Inverters; Power demand; Transistors; Adiabatic logic; CMOS; Odd parity; energy recovery; single phase;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Trends and Applications in Computer Science (ICETACS), 2013 1st International Conference on

Conference_Location

Shillong

Print_ISBN

978-1-4673-5249-9

Type

conf

DOI

10.1109/ICETACS.2013.6691397

Filename

6691397