Towards implementation of fault tolerant reversible circuits

Reversible computing is gaining importance in order to achieve low power consumption, high speed and packaging density in VLSI circuits. It has applications in various other fields such as quantum computing, nanotechnology, DNA computing, optical computing, cryptography and informatics. In order to achieve reliable circuits in reversible computing provision for fault tolerance is necessary. To achieve fault tolerance, the first stage is to identify occurrence of fault. To detect the occurrence, parity preserving technique has been reported in literature. This paper presents a new 4*4 parity preserving reversible logic gate PPTG (Parity Preserving Toffoli Gate) and its quantum realization. After that two new parity preserving implementations are presented in this paper. These implementations are used towards the development of fault tolerant reversible circuits. By which substitution becomes efficient and minimum in terms of constant inputs and garbage outputs. It permits us to use existing benchmarks preserving parity with only one additional circuit line.