A novel approach for and efficient implementation of 2 Level 2D DWT using ASIC and FPGA

In this paper, an efficient architecture called Modified Flipping is proposed. The implementation of 2 level 2D Discrete Wavelet Transform (DWT) is considered using Modified Flipping architecture. The System On Programmable Chip approach is adopted for the implementation of two level 2D DWT on Altera Field Programmable Gate Arrays based SOPC CYCLONE II EP2C35F672C6 kits with NIOS-II softcore processor. Modified flipping architecture and Flipping architecture are implemented using ASIC CADENCE TOOL of 180nm technology. From the implementation results, it is verified that the proposed Modified Flipping Architecture with MBW-PKCM increases the speed and reduce the hardware requirements. The proposed Modified flipping Architecture is operated with 6.8% higher speed compared with flipping Architecture. The hardware requirements are also 2% lesser compared to existing architecture. Pipelined registers required for MFA is 8.4% lesser than FA. Also for the sake of verification the proposed methods are verified using MATLAB R2009a. The corresponding output images for all the cases are given.