Title :
Using LV process to design high voltage DDDMOSFET and LDMOSFET with 3-D profile structure
Author :
Chien-Hao Huang ; Tsung-Yi Huang ; Ching-Yao Yang ; Huang-Ping Chu ; Kuo-Hsuan Lo ; Chung-Yu Hung ; Kuo-Cheng Chang ; Hung-Der Su ; Chih-Fang Huang ; Jeng Gong
Author_Institution :
Technol. Dev. Div., Richtek Technol. Corp., Hsinchu, Taiwan
Abstract :
In this work, layout skills using three dimensional (3D) fish bone, slot, and island patterns to enhance the breakdown voltage of PW/NW junction of lateral MOSFETs is developed. Novel lateral double diffused MOSFETs (LDMOSFET) and Double Diffused Drain MOSFETs (DDDMOSFET) without any high voltage (HV) layer are achieved in a standard 5V low voltage (LV) CMOS technology. From the experiment results, the developed DDDMOSFETs and LDMOSFETs can be used for 10V and 60V application respectively.
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit design; 3D profile structure; DDDMOSFET; LDMOSFET; LV process; PW-NW junction; breakdown voltage enhancement; double diffused drain MOSFET; island patterns; lateral double diffused MOSFET; layout skills; slot patterns; standard low voltage CMOS technology; three dimensional fish bone patterns; voltage 10 V; voltage 5 V; voltage 60 V; Bones; CMOS integrated circuits; Doping; Implants; Layout; Logic gates; Marine animals;
Conference_Titel :
Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on
Conference_Location :
Kanazawa
Print_ISBN :
978-1-4673-5134-8
DOI :
10.1109/ISPSD.2013.6694463
