A 75–90 GHz high linearity MMIC power amplifier with integrated output power detector

A four-stage power amplifier in the 75-90 GHz range with integrated output power detector has been designed and fabricated in a 0.1 μm GaAs pHEMT process. In-phase parallel combining is used in the last stages of the amplifier for increased output power and linearity. The chip exhibits 25 dB of gain and can deliver up to 19 dBm at the 1dB compression point, and 20 dBm when driven into saturation. The output third order intercept point (OIP3) of the amplifier is measured to be up to 29 dBm. The output voltage of the detector varies linearly by 1.5 V for 20 dB of output power range. The chip consumes less than 750 mW when fully driven into saturation and all transistors are biased with no more than 3.5 V for reliable operation.