A Reconfigurable HEVC sub-pixel interpolation hardware

Author

Kalali, Ercan ; Adibelli, Yusuf ; Hamzaoglu, Ilker

Author_Institution

Fac. of Eng. & Natural Sci., Sabanci Univ., Istanbul, Turkey

fYear

2013

fDate

9-11 Sept. 2013

Firstpage

125

Lastpage

128

Abstract

Sub-pixel interpolation is one of the most computationally intensive parts of High Efficiency Video Coding (HEVC) video encoder and decoder. Therefore, in this paper, a reconfigurable HEVC sub-pixel (half-pixel and quarter-pixel) interpolation hardware for all prediction unit sizes is proposed. The proposed reconfigurability reduces the area and power consumption of HEVC sub-pixel interpolation hardware more than 30%. The proposed hardware, in the worst case, can process 64 quad full HD (2560×1600) video frames per second.

Keywords

interpolation; video codecs; video coding; 64 quad full HD video frames; half-pixel interpolation hardware; high efficiency video coding; power consumption; quarter-pixel interpolation hardware; reconfigurable HEVC subpixel interpolation hardware; video decoder; video encoder; Decoding; Finite impulse response filters; Hardware; Interpolation; Power demand; Standards; Video coding; FPGA; HEVC; Hardware Implementation; Sub-pixel Interpolation;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics ?? Berlin (ICCE-Berlin), 2013. ICCEBerlin 2013. IEEE Third International Conference on

Conference_Location

Berlin

Print_ISBN

978-1-4799-1411-1

Type

conf

DOI

10.1109/ICCE-Berlin.2013.6698023

Filename

6698023