Impact of integrating microchannel cooling within 3D microelectronic packages for portable applications

This work presents the impact of integrating microfluidic channels at different locations in a 3D stacked chip configuration to improve its thermal management. Bringing fluidic cooling within the microelectronic package can allow the use of higher power chips in limited space applications, but suitable sites for the microchannels in packaged 3D stacks must be determined. The approach uses an analytical representation of microfluidics and heat transfer at the package level to evaluate the equivalent thermal resistances. This analytical lumped-element circuit model is used to compare different microchannel cooling configurations, for 3D stacked chips. With the addition of microfluidic cooling, the allowable power level increases dramatically. The study also shows that locating the fluid cooling inside or adjacent to the chip stack reduces the thermal resistance over 6 times compared to microchannels located at the surface of the molding or the ball grid array. Within the chip stack however, the location does not have a noticeable impact. The actual thermal design power of microprocessors for portable applications has the potential to be doubled by using microfluidic cooling with moderate flow rates and pressure drops.