DocumentCode :
665326
Title :
Heterogeneous wafer reconstruction and wafer level hybridization by copper direct bonding for Infrared imagers
Author :
Mani, Abdenacer Ait ; Huet, S.
Author_Institution :
LETI, CEA, Grenoble, France
fYear :
2013
fDate :
9-12 Sept. 2013
Firstpage :
1
Lastpage :
8
Abstract :
The manufacturing technology of Infrared imagers suffers since the beginning of a lack of competitiveness compared to the Silicon based manufacturing technologies (wafer sizes, yield, volumes produced...). A special care is needed for the manipulation of wafers which are more fragile than Silicon due to their metallurgical composition. The mass, greater than Silicon act often as a limitation factor when a quick automatic manipulation is needed. The study we have undertaken and described in this paper shows that it is possible to reduce the gap between the IR and the Silicon Fields by processing directly a III-V substrate on a standard Silicon production line (200 or 300 mm). The obtained results are very encouraging for a so initial big challenge. In order to do that, it is necessary to build a heterogeneous wafer so that the assembly can act as a transparent new wafer for all the operations of Oxide deposition, metals deposition, photolithography, etching, CMP, cleaning, direct bonding with alignment procedure, thermal annealing, Grinding, Polishing, Final dicing and test. Finally, one of the most difficult parameter to conform to our need was the process temperatures, we lead in that way a manufacturing process flow respecting the maximum temperature which does not degrade the integrity of potential photodiodes present onto the InSb substrate. From the first transfer of the InSb substrate on the Silicon Host until the final annealing of the direct bonding assembly, all the operations were done along a temperature process flow under 300°C.
Keywords :
III-V semiconductors; annealing; bonding processes; chemical mechanical polishing; copper; elemental semiconductors; etching; grinding; indium compounds; infrared detectors; photodiodes; photolithography; silicon; surface cleaning; vapour deposition; CMP; InSb; chemical mechanical polishing; cleaning; copper direct bonding; etching; final dicing; grinding; heterogeneous wafer reconstruction; infrared imagers; manufacturing process flow; metals deposition; oxide deposition; photodiodes; photolithography; plasma enhanced chemical vapour deposition; silicon production line; size 200 nm; size 300 nm; temperature 300 degC; thermal annealing; wafer level hybridization; Assembly; Bonding; Copper; Semiconductor device modeling; Silicon; Substrates; CMP (Chemical and Mechanical Polishing); CTE(Coefficient of Thermal Expansion); Direct Bonding; ECD (Electro Chemical Deposition); Grinding; Heterogeneous wafers; PECVD (Plasma Enhanced Chemical Vapor Deposition); reconstructed wafers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronics Packaging Conference (EMPC) , 2013 European
Conference_Location :
Grenoble
Type :
conf
Filename :
6698645
Link To Document :
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