DocumentCode
666102
Title
System-on-Chip implementation of Reliable Ethernet Networks nodes
Author
Astarloa, Armando ; Lazaro, J. ; Bidarte, Unai ; Zuloaga, Aitzol ; Idirin, Mikel
Author_Institution
Fac. of Eng., Univ. of the Basque Country, Bilbao, Spain
fYear
2013
fDate
10-13 Nov. 2013
Firstpage
2329
Lastpage
2334
Abstract
Reliable Ethernet Networks are gaining acceptance for many Industrial Automation applications. However, the diversity and variety of emerging Ethernet based Industrial Protocols make difficult for the Industry the selection of the technology to implement them. Furthermore, the continue evolution of the standards and their combination increment the risk in the engineering decisions. This need for flexibility combined with the need for hardware processing make FPGAs and reconfigurable devices in general, the best candidates to implement network devices and equipments able to deal with these issues. In this work, 3 architectures for Reliable Network Devices that support HSR and PRP protocols are presented. These architectures benefit from cutting-edge 28nm silicon fabrication reconfigurable technology combined with on-chip ARM processors and peripheral. One of the proposed architectures is implemented following a Design Flow that integrates 3 complex EDA tools and a third-party IP to achieve a full operative Reliable Networking Device with HSR and PRP processing capabilities.
Keywords
computer network reliability; field programmable gate arrays; local area networks; protocols; reconfigurable architectures; redundancy; system-on-chip; EDA tools; Ethernet based industrial protocols; HSR processing capabilities; HSR protocols; PRP processing capabilities; PRP protocols; cutting-edge silicon fabrication reconfigurable technology; hardware processing; high-availability seamless redundancy protocol; industrial automation applications; on-chip ARM peripheral; on-chip ARM processors; parallel redundancy protocol; reconfigurable devices; reliable Ethernet network nodes; reliable network devices; system-on-chip implementation; third-party IP; IP networks; Ports (Computers); Program processors; Protocols; Redundancy; System-on-chip; High-availability Seamless Redundancy (HSR); IEC 61850; Parallel Redundancy Protocol (PRP) FPGA; Reliable Ethernet; SoC; Zynq;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Electronics Society, IECON 2013 - 39th Annual Conference of the IEEE
Conference_Location
Vienna
ISSN
1553-572X
Type
conf
DOI
10.1109/IECON.2013.6699494
Filename
6699494
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