Efficient non-iterative fixed-period SVM training architecture for FPGAs

A method for efficient non-iterative fixed-period SVM training is presented. A highly pipelined, parallel, and concurrent systolic processing-based hardware architecture overview for FPGA implementation is also provided. The architecture´s training performance is simulated in software and tested successfully by solving two classification problems utilising a 2-dimensional linearly-separable dataset and a 2-dimensional XOR-problem dataset. In both cases the trained optimal SVM function-model classified both datasets with 100% accuracy and thus verified the training architecture´s feasibility and potential for further investigation and FPGA implementation.