Low-power hardware implementation of noise tolerant heart rate extractor for a wearable monitoring system

To prevent lifestyle diseases, wearable bio-signal monitoring systems for daily life monitoring have attracted attention. Wearable systems have strict size and weight constraints, which impose significant limitations of the battery capacity and the signal-to-noise ratio of bio-signals. The novelty of this work is the hardware implementation of a noise-tolerant heart rate extraction algorithm that can achieve low-power performance with high reliability. This report describes comparisons of the heart rate extraction algorithm performance and the dedicated hardware implementation of short-term autocorrelation (STAC) method. The proposed heart rate extractor, implemented in 65-nm CMOS process using Verilog-HDL, consumes 1.65 μA at 32.768-kHz operating frequency with 1.1 V supply voltage.