Critical path analysis of two-channel interleaved digital MASH ΔΣ modulators

Implementation of wireless wideband transmitters using ΔΣ DACs requires very high speed modulators. Digital MASH ΔΣ modulators are good candidates for speed enhancement using interleaving because they require only adders and can be cascaded. This paper presents an analysis of the integrator critical path of two-channel interleaved ΔΣ modulators. The bottlenecks for a high-speed operation are identified and the performance of different logic styles is compared. Static combinational logic shows the best trade-off and potential for use in such high speed modulators. A prototype 12-bit second order MASH ΔΣ modulator designed in 65 nm CMOS technology based on this study achieves 9 GHz operation at 1 V supply.