A 7-bit 50ms/s single-ended asynchronous SAR ADC in 65nm CMOS

This paper presents a 7-bit 50MS/s single-ended asynchronous SAR ADC intended for in-probe use in some ultrasound imaging system. It aims at low power, small area and moderate resolution. Relaxed by a moderate resolution, a single-ended architecture with a double reference technique is proposed to improve the power efficiency and reduce active area, which are limited by the minimum dimension of the technology. Also, a delay line with tunable and asymmetric characteristics is proposed to be embedded in the asynchronous digital logic, enabling high speed at 50MS/s. Simulations show that the prototype designed in a 65nm CMOS technology achieves an SNDR of 42.7dB and an ENOB of 6.8bit at a sampling frequency of 50MS/s while consuming 157μW from a IV supply, resulting in an energy efficiency of 28fJ/conversion-step. The core circuit layout only occupies 0.017mm².