A 31.25/125MSps continuous-time ΔΣ ADC with 64/59db SNDR in 130nm CMOS

Author

Shubo Yan ; Andersson, Mats ; Sjoland, Henrik

Author_Institution

Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden

fYear

2013

fDate

11-12 Nov. 2013

Firstpage

1

Lastpage

4

Abstract

A 2^nd order 3-bit continuous-time (CT) ΔΣ ADC is presented in this paper. The design equations starting from a discrete-time reference modulator to the circuit implementation are given. The non-return to zero (NRZ) DAC pulses have a half clock cycle loopdelay which is corrected by the feedforward (also known as PI) loop delay compensation, and nonlinearities in the DACs are suppressed by data-weighted averaging. The fabricated 130nm design operates at 31.25/125MHz at a power consumption of 6.04/6.32mA from a 1.2V supply, and achieves an SNDR of 64/59dB at an OSR of 32, resulting in an FOM of 5.73/2.67pJ/cony. step.

Keywords

CMOS digital integrated circuits; delta-sigma modulation; integrated circuit design; CMOS tecgnology; DAC nonlinearities; NRZ DAC pulses; circuit implementation; continuous-time ΔΣ ADC; current 6.04 mA; current 6.32 mA; data-weighted averaging; design equation; discrete-time reference modulator; feedforward loop delay compensation; half-clock cycle loopdelay; nonreturn-to-zero DAC pulses; second-order 3-bit CT ΔΣ ADC; size 130 nm; voltage 1.2 V; Clocks; Delays; Feedforward neural networks; Modulation; Optical signal processing; Prototypes; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

NORCHIP, 2013

Conference_Location

Vilnius

Type

conf

DOI

10.1109/NORCHIP.2013.6702021

Filename

6702021