Correlator design and implementation for GNSS receivers

This paper shows how the correlator block for GNSS receivers can be analyzed and optimized. The received signal characteristics are reviewed and used in the optimization process. The correlator is a key element in the GNSS receivers and it takes a considerable amount of the chip area and power. It is shown that a gate-count reduction of 30% or more can be achieved while also reducing the power consumption by more than 50%. The authors also discuss how advanced functionality can be added with just a minor increase of the correlator gate-count. The additional logic allows real-time configuration of the correlator hardware, which increases its usability in advanced GNSS receivers.