• DocumentCode
    667996
  • Title

    Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV

  • Author

    Murugesan, Mariappan ; Bea, J.C. ; Lee, Kuan Waey ; Fukushima, Tetsuya ; Tanaka, T. ; Koyanagi, Mitsumasa ; Sutou, Y. ; Wang, Huifang ; Koike, Junichi

  • Author_Institution
    NICHe, Tohoku Univ., Sendai, Japan
  • fYear
    2013
  • fDate
    2-4 Oct. 2013
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    The effectiveness of thermal chemical-vapor-deposited (CVD) manganese oxide (MnOx) for their application in the copper (Cu)-through-silicon-via (TSV) structure as a barrier layer was investigated by X-ray photo-electron spectroscopy (XPS), transmission electron spectroscopy (TEM), and capacitance-voltage (C-V) measurements. TEM data revealed the conformal growth of 20 nm-thick MnOx on the surface of plasma-TEOS SiO2 in the sidewall of TSV by thermal CVD. An excellent barrier property for MnOx over the thermal SiO2 was confirmed up to the maximum annealing temperature of 500°C. In the case of plasma-TEOS SiO2, the barrier property was good up to 400°C, but beyond that temperature, the barrier property was found deteriorated. On the contrary, the barrier performance of MnOx grown on the surface of ozone-TEOS SiO2 was found to be negligibly small. Even at room-temperature, we did observe the Cu2p signal emanating from MnOx/SiO2 region. Therefore, care must be taken while using either MnOx as a barrier layer upon ozone-TEOS SiO2 or ozone-TEOS SiO2 itself as a dielectric liner in along the side wall of TSVs, before integrating them into 3D-LSIs.
  • Keywords
    X-ray photoelectron spectra; annealing; chemical vapour deposition; copper; diffusion; integrated circuit interconnections; large scale integration; manganese compounds; silicon compounds; three-dimensional integrated circuits; transmission electron microscopy; 3D-LSI; Cu; MnO; SiO2; TEM; TSV structure; X-ray photoelectron spectroscopy; XPS; annealing; barrier layer; capacitance-voltage measurements; diffusion barrier; oxide layer; size 20 nm; temperature 400 degC; temperature 500 degC; thermal CVD; thermal chemical vapor deposition; through silicon via; transmission electron spectroscopy; Annealing; Capacitance-voltage characteristics; Manganese; Plasma temperature; Silicon; Through-silicon vias; Barrier layer; Cu-diffusion; MnOx; TSV; XPS;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    3D Systems Integration Conference (3DIC), 2013 IEEE International
  • Conference_Location
    San Francisco, CA
  • Type

    conf

  • DOI
    10.1109/3DIC.2013.6702364
  • Filename
    6702364